DEFECT-ORIENTED TESTING FOR NANO-METRIC CMOS VLSI CIRCUITS by Manoj Sachdev, Jose Pineda de Gyvez ( 9781441942852 )

Item Details

Title:

DEFECT-ORIENTED TESTING FOR NANO-METRIC CMOS VLSI CIRCUITS

By:

Format:

Paperback

List price:	£129.99
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ISBN 10:

1441942858

ISBN 13:

9781441942852

Publisher:

SPRINGER-VERLAG NEW YORK INC.

Pub. date:

12 February, 2010

Edition:

Softcover reprint of hardcover 2nd ed. 2007

Series:

Frontiers in Electronic Testing 34

Pages:

328

Synopsis:

The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.

Illustrations:

XXI, 328 p.

Publication:

Imprint:

Springer-Verlag New York Inc.

Returns:

Returnable

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CMOS SRAM CIRCUIT DESIGN AND PARAMETRIC TEST IN NANO-SCALED TECHNOLOGIES (PB)

DEFECT ORIENTED TESTING FOR CMOS ANALOG AND DIGITAL CIRCUITS (HB)

DEFECT-ORIENTED TESTING FOR NANO-METRIC CMOS VLSI CIRCUITS (HB)