NANO-CMOS DESIGN FOR MANUFACTURABILITY by Ban P. Wong, Anurag Mittal, Greg W. Starr ( 9780470112809 )

Item Details

Title:

NANO-CMOS DESIGN FOR MANUFACTURABILITY
ROBUST CIRCUIT AND PHYSICAL DESIGN FOR SUB-65NM TECHNOLOGY NODES

By:

Ban P. Wong, Anurag Mittal, Greg W. Starr

Format:

Hardback

List price:

£116.95

Our price:

£105.26

Discount:

10% off

You save:

£11.69

ISBN 10:

0470112808

ISBN 13:

9780470112809

Availability:

Usually dispatched within 1-3 weeks.

Delivery rates

Stock:

Currently 0 available

Publisher:

JOHN WILEY AND SONS LTD

Pub. date:

1 November, 2008

Pages:

386

Description:

The current semiconductor model continues to give birth to a large number of design engineers who are producing a large number of chips, but without any interaction with process/device people. This book addresses major challenges faced by engineers and offers concrete solutions provided by industry experts.

Synopsis:

Discover innovative tools that pave the way from circuit and physical design to fabrication processing Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to discussing the difficulties brought on by the continued dimensional scaling in conformance with Moore's law, the authors also tackle complex issues in the design process to overcome the difficulties, including the use of a functional first silicon to support a predictable product ramp. Moreover, they introduce several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions. This book is the sequel to Nano-CMOS Circuit and Physical Design, taking design to technology nodes beyond 65nm geometries.It is divided into three parts: Part One, Newly Exacerbated Effects, introduces the newly exacerbated effects that require designers' attention, beginning with a discussion of the lithography aspects of DFM, followed by the impact of layout on transistor performance Part Two, Design Solutions, examines how to mitigate the impact of process effects, discussing the methodology needed to make sub-wavelength patterning technology work in manufacturing, as well as design solutions to deal with signal, power integrity, WELL, stress proximity effects, and process variability Part Three, The Road to DFM, describes new tools needed to support DFM efforts, including an auto-correction tool capable of fixing the layout of cells with multiple optimization goals, followed by a look ahead into the future of DFM Throughout the book, real-world examples simplify complex concepts, helping readers see how they can successfully handle projects on Nano-CMOS nodes.It provides a bridge that allows engineers to go from physical and circuit design to fabrication processing and, in short, make designs that are not only functional, but that also meet power and performance goals within the design schedule.

Illustrations:

Illustrations

Publication:

Imprint:

Wiley-Blackwell

Returns:

Returnable

Some other items by this author:

DECKEN

DECKEN (HB)

FLACHDACH

FLACHDACH (HB)