LOW-POWER DEEP SUB-MICRON CMOS LOGIC by P. van der Meer, A. van Staveren, Arthur H. M. van Roermund ( 9781402028489 )

Item Details

Title:

LOW-POWER DEEP SUB-MICRON CMOS LOGIC
SUB-THRESHOLD CURRENT REDUCTION

By:

P. van der Meer, A. van Staveren, Arthur H. M. van Roermund

Format:

Mixed media product

List price:	£73.44
We currently do not stock this item, please contact the publisher directly for further information.

ISBN 10:

1402028482

ISBN 13:

9781402028489

Publisher:

SPRINGER-VERLAG NEW YORK INC.

Pub. date:

19 November, 2004

Edition:

2004 ed.

Series:

The Springer International Series in Engineering and Computer Science 841

Pages:

154

Description:

The strong interaction between the demand for increasing chip functionality and data-processing speeds and technological trends in the integrated circuit industry cause a huge increase in power dissipation. This book classifies all power dissipation sources in digital CMOS circuits and provides a systematic approach of power reduction techniques.

Synopsis:

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in- dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi- pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa- gation delay, which results in a lower data-processing speed performance.

Illustrations:

128 Illustrations, black and white; XIV, 154 p. 128 illus. With CD-ROM.

Publication:

Imprint:

Springer-Verlag New York Inc.

Returns:

Non-returnable

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