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Item Details
| Title:
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HIGH-LEVEL ESTIMATION AND EXPLORATION OF RELIABILITY FOR MULTI-PROCESSOR SYSTEM-ON-CHIP
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| By: |
Zheng Wang, Anupam Chattopadhyay |
| Format: |
Hardback |
| List price:
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£109.99 |
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We believe that this item is permanently unavailable, and so we cannot source
it.
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| ISBN 10: |
9811010722 |
| ISBN 13: |
9789811010729 |
| Publisher: |
SPRINGER VERLAG, SINGAPORE |
| Pub. date: |
5 July, 2017 |
| Edition: |
1st ed. 2018 |
| Series: |
Computer Architecture and Design Methodologies |
| Pages: |
197 |
| Synopsis: |
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. |
| Illustrations: |
80 Tables, color; 72 Illustrations, color; 32 Illustrations, black and |
| Publication: |
Singapore |
| Imprint: |
Springer Verlag, Singapore |
| Returns: |
Returnable |
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