MODELING OF ELECTRICAL OVERSTRESS IN INTEGRATED CIRCUITS by Carlos H. Diaz, Sung-Mo Kang ( 9780792395058 )

Item Details

Title:

MODELING OF ELECTRICAL OVERSTRESS IN INTEGRATED CIRCUITS

By:

Format:

Hardback

List price:	£171.00
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ISBN 10:

0792395050

ISBN 13:

9780792395058

Publisher:

SPRINGER

Pub. date:

3 November, 1994

Edition:

1995 ed.

Series:

The Springer International Series in Engineering and Computer Science 289

Pages:

148

Description:

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose as one of the threats to integrated circuits (ICs). This book analyzes the EOS/ESD-related failures in I/O protection devices in integrated circuits. This book is intended for VLSI designers, reliability engineers and those working on the development of EOS/ESD analysis tools.

Synopsis:

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure. Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields.

Illustrations:

XXV, 148 p.

Publication:

Netherlands

Imprint:

Springer

Returns:

Returnable

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