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Item Details
Title: ADVANCED BDD OPTIMIZATION
By: Rudiger Ebendt, Gorschwin Fey, Rolf Drechsler
Format: Paperback

List price: £109.99


We currently do not stock this item, please contact the publisher directly for further information.

ISBN 10: 144193796X
ISBN 13: 9781441937964
Publisher: SPRINGER-VERLAG NEW YORK INC.
Pub. date: 12 October, 2010
Edition: 1st ed. Softcover of orig. ed. 2005
Pages: 222
Synopsis: VLSI CADhas greatly bene?ted from the use of reduced ordered Binary Decision Diagrams (BDDs) and the clausal representation as a problem of Boolean Satis?ability (SAT), e.g. in logic synthesis, ver- cation or design-for-testability. In recent practical applications, BDDs are optimized with respect to new objective functions for design space exploration. The latest trends show a growing number of proposals to fuse the concepts of BDD and SAT. This book gives a modern presentation of the established as well as of recent concepts. Latest results in BDD optimization are given, c- ering di?erent aspects of paths in BDDs and the use of e?cient lower bounds during optimization. The presented algorithms include Branch ? and Bound and the generic A -algorithm as e?cient techniques to - plore large search spaces. ? The A -algorithm originates from Arti?cial Intelligence (AI), and the EDA community has been unaware of this concept for a long time. Re- ? cently, the A -algorithm has been introduced as a new paradigm to explore design spaces in VLSI CAD. Besides AI search techniques, the book also discusses the relation to another ?eld of activity bordered to VLSI CAD and BDD optimization: the clausal representation as a SAT problem.
Illustrations: biography
Publication: US
Imprint: Springer-Verlag New York Inc.
Returns: Returnable
Some other items by this author:
ADVANCED BDD OPTIMIZATION (HB)
ADVANCED FORMAL VERIFICATION (HB)
ADVANCED FORMAL VERIFICATION (PB)
ADVANCED LOGIC SYNTHESIS (HB)
AUTOMATED ANALYSIS OF VIRTUAL PROTOTYPES AT THE ELECTRONIC SYSTEM LEVEL
AUTOMATED ANALYSIS OF VIRTUAL PROTOTYPES AT THE ELECTRONIC SYSTEM LEVEL (HB)
AUTOMATED VALIDATION & VERIFICATION OF UML/OCL MODELS USING SATISFIABILITY SOLVERS
AUTOMATED VALIDATION & VERIFICATION OF UML/OCL MODELS USING SATISFIABILITY SOLVERS (HB)
AUTOMATIC METHODS FOR THE REFINEMENT OF SYSTEM MODELS (PB)
BINARY DECISION DIAGRAMS (HB)
BINARY DECISION DIAGRAMS (PB)
COMPUTER (PB)
DEBUG AUTOMATION FROM PRE-SILICON TO POST-SILICON (HB)
DEBUG AUTOMATION FROM PRE-SILICON TO POST-SILICON (PB)
DEBUGGING AT THE ELECTRONIC SYSTEM LEVEL (HB)
DEBUGGING AT THE ELECTRONIC SYSTEM LEVEL (PB)
DESIGN AUTOMATION FOR FIELD-COUPLED NANOTECHNOLOGIES
DESIGN AUTOMATION FOR FIELD-COUPLED NANOTECHNOLOGIES (HB)
DESIGN AUTOMATION TECHNIQUES FOR APPROXIMATION CIRCUITS (HB)
DESIGN AUTOMATION TECHNIQUES FOR APPROXIMATION CIRCUITS (PB)
DESIGN FOR TESTABILITY, DEBUG AND RELIABILITY
DESIGN FOR TESTABILITY, DEBUG AND RELIABILITY (HB)
ENHANCED VIRTUAL PROTOTYPING
ENHANCED VIRTUAL PROTOTYPING (HB)
ENHANCED VIRTUAL PROTOTYPING FOR HETEROGENEOUS SYSTEMS (HB)
EVOLUTIONARY ALGORITHMS FOR EMBEDDED SYSTEM DESIGN (HB)
EVOLUTIONARY ALGORITHMS FOR EMBEDDED SYSTEM DESIGN (PB)
EVOLUTIONARY ALGORITHMS FOR VLSI CAD (HB)
EVOLUTIONARY ALGORITHMS FOR VLSI CAD (PB)
EXACT DESIGN OF DIGITAL MICROFLUIDIC BIOCHIPS (HB)
EXACT DESIGN OF DIGITAL MICROFLUIDIC BIOCHIPS (PB)
FORMAL MODELING AND VERIFICATION OF CYBER-PHYSICAL SYSTEMS (PB)
FORMAL SPECIFICATION LEVEL (HB)
FORMAL SPECIFICATION LEVEL (PB)
FORMAL SYSTEM VERIFICATION (HB)
FORMAL VERIFICATION OF CIRCUITS (HB)
FORMAL VERIFICATION OF CIRCUITS (PB)
FORMAL VERIFICATION OF STRUCTURALLY COMPLEX MULTIPLIERS
FORMAL VERIFICATION OF STRUCTURALLY COMPLEX MULTIPLIERS (HB)
GRAPHENBASIERTE FUNKTIONSDARSTELLUNG
HIGH QUALITY TEST PATTERN GENERATION AND BOOLEAN SATISFIABILITY (HB)
HIGH QUALITY TEST PATTERN GENERATION AND BOOLEAN SATISFIABILITY (PB)
IN-MEMORY COMPUTING (HB)
INTRODUCTION TO REVERSIBLE AND QUANTUM CIRCUITS (HB)
LANGUAGES, DESIGN METHODS, AND TOOLS FOR (PB)
LANGUAGES, DESIGN METHODS, AND TOOLS FOR ELECTRONIC SYSTEM DESIGN (HB)
METHODEN UND BESCHREIBUNGSSPRACHEN ZUR MODELLIERUNG UND VERIFIKATION VON SCHALTUNGEN UND SYSTEMEN (PB)
NOCH ANALOG ODER LEBST DU SCHON?
QUALITY-DRIVEN SYSTEMC DESIGN (HB)
QUALITY-DRIVEN SYSTEMC DESIGN (PB)
REVERSIBLE AND QUANTUM CIRCUITS (HB)
ROBUSTNESS AND USABILITY IN MODERN DESIGN FLOWS (HB)
ROBUSTNESS AND USABILITY IN MODERN DESIGN FLOWS (PB)
SPECTRAL TECHNIQUES IN VLSI CAD (HB)
SPECTRAL TECHNIQUES IN VLSI CAD (PB)
TEST DIGITALER SCHALTKREISE
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TEST PATTERN GENERATION USING BOOLEAN PROOF ENGINES (HB)
TEST PATTERN GENERATION USING BOOLEAN PROOF ENGINES (PB)
TOWARDS A DESIGN FLOW FOR REVERSIBLE LOGIC (HB)
TOWARDS A DESIGN FLOW FOR REVERSIBLE LOGIC (PB)
TOWARDS ONE-PASS SYNTHESIS (HB)
TOWARDS ONE-PASS SYNTHESIS (HB)
TOWARDS ONE-PASS SYNTHESIS (PB)
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