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Item Details
Title: WAFER-LEVEL CHIP-SCALE PACKAGING
ANALOG AND POWER SEMICONDUCTOR APPLICATIONS
By: Shichun Qu
Format: Paperback

List price: £89.99


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ISBN 10: 1493954385
ISBN 13: 9781493954384
Publisher: SPRINGER-VERLAG NEW YORK INC.
Pub. date: 3 August, 2016
Edition: Softcover reprint of the original 1st ed. 2015
Pages: 322
Description: This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ] Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ] Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology ] Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLs.
Synopsis: Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design.An overview of the analog and power WLCSP modeling and typical thermal, electrical and stress modeling methodologies is also presented in the book.
Illustrations: 58 black & white illustrations, 256 colour illustrations, 58 black & white
Publication: US
Imprint: Springer-Verlag New York Inc.
Returns: Returnable
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WAFER-LEVEL CHIP-SCALE PACKAGING (HB)

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