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Item Details
Title: TRANSACTIONAL MEMORY
By: Jim Larus, Ravi Rajwar, Mark D. Hill
Format: Paperback

List price: £37.95


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ISBN 10: 1598291246
ISBN 13: 9781598291247
Publisher: MORGAN & CLAYPOOL PUBLISHERS
Pub. date: 21 November, 2006
Series: Synthesis Lectures on Computer Architecture
Pages: 226
Description: The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This book offers an alternative way to coordinate concurrent threads. It provides an overview of the design and implementation of transactional memory systems.
Synopsis: The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, runtime system, and hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure.This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early summer 2006.
Illustrations: Illustrations
Publication: US
Imprint: Morgan & Claypool Publishers
Returns: Non-returnable
Some other items by this author:
A FOUNDATION FOR TRANSFORMING PROGRAMS FOR PARALLEL EXECUTION (PB)
A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE (PB)
COMPUTER ARCHITECTURE TECHNIQUES FOR POWER EFFICIENCY (PB)
DESIGN VARIABILITY (PB)
FAULT TOLERANT COMPUTER ARCHITECTURE (PB)
MULTI-CORE CACHE HIERARCHIES (PB)
ON-CHIP NETWORKS (PB)
PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE (HB)
PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE, SECOND EDITION
QUANTUM COMPUTING FOR COMPUTER ARCHITECTS (PB)
READINGS IN COMPUTER ARCHITECTURE (PB)
RESILIENT ARCHITECTURE DESIGN FOR VOLTAGE VARIATION (PB)
RESILIENT SYSTEM DESIGN (PB)
SYNTHESIS SERIES IN COMPUTER AND INFORMATION SCIENCE (HB)
THE MEMORY SYSTEM (PB)
TRANSACTIONAL MEMORY
TRANSACTIONAL MEMORY (PB)
TRANSACTIONAL MEMORY, 2ND EDITION
TRANSACTIONAL MEMORY, SECOND EDITION

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