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Item Details
| Title:
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ON-CHIP NETWORKS
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| By: |
Natalie D. Enright Jerger, Li-Shiuan Peh, Mark D. Hill |
| Format: |
Paperback |
| List price:
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£37.95 |
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We currently do not stock this item, please contact the publisher directly for
further information.
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| ISBN 10: |
1598295845 |
| ISBN 13: |
9781598295849 |
| Publisher: |
MORGAN & CLAYPOOL PUBLISHERS |
| Pub. date: |
1 June, 2008 |
| Series: |
Synthesis Lectures on Computer Architecture |
| Pages: |
141 |
| Description: |
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication is increasingly important. This volume examines various fundamental aspects of on-chip network design and provides the reader with an overview of the current state-of-the-art research in this field. |
| Synopsis: |
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. |
| Illustrations: |
black & white illustrations |
| Publication: |
US |
| Imprint: |
Morgan & Claypool Publishers |
| Returns: |
Non-returnable |
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