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Item Details
Title: ROUTING CONGESTION IN VLSI CIRCUITS
ESTIMATION AND OPTIMIZATION
By: Sachin S. Sapatnekar, Prashant Saxena, Rupesh S. Shelar
Format: Hardback

List price: £139.99


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ISBN 10: 0387300376
ISBN 13: 9780387300375
Publisher: SPRINGER-VERLAG NEW YORK INC.
Pub. date: 18 April, 2007
Series: Integrated Circuits and Systems
Pages: 250
Description: This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques.
Synopsis: This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
Illustrations: XIV, 250 p.
Publication: US
Imprint: Springer-Verlag New York Inc.
Returns: Returnable
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