THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN by Yuan Xie (Editor), Jason Cong (Editor), Sachin S. Sapatnekar (Editor) ( 9781441907837 )

Item Details

Title:

THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN
EDA, DESIGN AND MICROARCHITECTURES

By:

Yuan Xie (Editor), Jason Cong (Editor), Sachin S. Sapatnekar (Editor)

Format:

Hardback

List price:	£139.99
We currently do not stock this item, please contact the publisher directly for further information.

ISBN 10:

1441907831

ISBN 13:

9781441907837

Publisher:

SPRINGER-VERLAG NEW YORK INC.

Pub. date:

10 December, 2009

Edition:

2010 ed.

Series:

Integrated Circuits and Systems

Pages:

284

Description:

This book presents an overview of the field of 3D IC design. There is emphasis on electronic design automation (EDA) tools and algorithms that can enable the adoption of 3D ICs, and the architectural implementation and potential for future 3D system design.

Synopsis:

We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore's law. This observation stated that transistor density in integrated circuits doubles every 1. 5-2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore's law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).

Illustrations:

35 Tables, black and white; XII, 284 p.

Publication:

Imprint:

Springer-Verlag New York Inc.

Returns:

Returnable

Some other items by this author:

CUSTOMIZABLE COMPUTING

CUSTOMIZABLE COMPUTING (PB)

DESIGN AUTOMATION FOR TIMING-DRIVEN LAYOUT SYNTHESIS (HB)

DESIGN AUTOMATION FOR TIMING-DRIVEN LAYOUT SYNTHESIS (PB)