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Item Details
Title: CROSS-TALK NOISE IMMUNE VLSI DESIGN USING REGULAR LAYOUT FABRICS
By: Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Format: Paperback

List price: £89.99


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ISBN 10: 1461355737
ISBN 13: 9781461355731
Publisher: SPRINGER-VERLAG NEW YORK INC.
Pub. date: 30 June, 2001
Edition: Softcover reprint of the original 1st ed. 2001
Pages: 112
Synopsis: This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our approach, we ensure that cross-talk is eliminated by design. The work described in this book attempts to take an "outside-the-box" view and propose a radically different design style. This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes. With our choice of fabric, cross-talk between adjacent wires on an IC is reduced by between one and two orders of magnitude.In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. The first flow uses fabric-compliant standard cells as an im- plementation vehicle. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared.
Illustrations: biography
Publication: US
Imprint: Springer-Verlag New York Inc.
Returns: Returnable
Some other items by this author:
ALGORITHMS FOR SYNTHESIS AND TESTING OF ASYNCHRONOUS CIRCUITS (HB)
ALGORITHMS FOR SYNTHESIS AND TESTING OF ASYNCHRONOUS CIRCUITS (PB)
CROSS-TALK NOISE IMMUNE VLSI DESIGN USING REGULAR LAYOUT FABRICS (HB)
DESIGN SYSTEMS FOR VLSI CIRCUITS (HB)
DESIGN SYSTEMS FOR VLSI CIRCUITS (PB)
FUNCTION/ARCHITECTURE OPTIMIZATION AND CO-DESIGN OF EMBEDDED SYSTEMS (HB)
FUNCTION/ARCHITECTURE OPTIMIZATION AND CO-DESIGN OF EMBEDDED SYSTEMS (PB)
HYBRID SYSTEMS - COMPUTATION AND CONTROL (PB)
INTEGRATING FUNCTIONAL AND TEMPORAL DOMAINS IN LOGIC DESIGN (HB)
INTEGRATING FUNCTIONAL AND TEMPORAL DOMAINS IN LOGIC DESIGN (PB)
LOGIC MINIMIZATION ALGORITHMS FOR VLSI SYNTHESIS (HB)
LOGIC MINIMIZATION ALGORITHMS FOR VLSI SYNTHESIS (PB)
LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS (HB)
LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS (PB)
NOISE ANALYSIS OF RADIO FREQUENCY CIRCUITS (HB)
NOISE ANALYSIS OF RADIO FREQUENCY CIRCUITS (PB)
PLATFORM-BASED DESIGN (HB)
REGULAR FABRICS IN DEEP SUB-MICRON INTEGRATED-CIRCUIT DESIGN (HB)
REGULAR FABRICS IN DEEP SUB-MICRON INTEGRATED-CIRCUIT DESIGN (PB)
RELAXATION TECHNIQUES FOR THE SIMULATION OF VLSI CIRCUITS (HB)
RELAXATION TECHNIQUES FOR THE SIMULATION OF VLSI CIRCUITS (PB)
STEADY-STATE METHODS FOR SIMULATING ANALOG AND MICROWAVE CIRCUITS (HB)
STEADY-STATE METHODS FOR SIMULATING ANALOG AND MICROWAVE CIRCUITS (PB)
SYNCHRONOUS EQUIVALENCE (PB)
SYNTHESIS OF FINITE STATE MACHINES (HB)
SYNTHESIS OF FINITE STATE MACHINES (HB)
SYNTHESIS OF FINITE STATE MACHINES (PB)
SYNTHESIS OF FINITE STATE MACHINES (PB)
THE UNKNOWN COMPONENT PROBLEM (HB)
THE UNKNOWN COMPONENT PROBLEM (PB)
TIMED BOOLEAN FUNCTIONS (HB)
TIMED BOOLEAN FUNCTIONS (PB)

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