| Title:
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DESIGN-FOR-TEST AND TEST OPTIMIZATION TECHNIQUES FOR TSV-BASED 3D STACKED ICS
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| By: |
Brandon Noia, Krishnendu Chakrabarty |
| Format: |
Paperback |
| List price:
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£79.99 |
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| ISBN 10: |
3319345346 |
| ISBN 13: |
9783319345345 |
| Publisher: |
SPRINGER INTERNATIONAL PUBLISHING AG |
| Pub. date: |
23 August, 2016 |
| Edition: |
Softcover reprint of the original 1st ed. 2014 |
| Pages: |
245 |
| Description: |
This volume encompasses the latest, innovative methods of testing three-dimensional integrated circuits, incorporating pre-bond and post-bond tests as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective. |
| Synopsis: |
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. |
| Illustrations: |
23 Tables, black and white; 115 Illustrations, color; 18 Illustrations, |
| Publication: |
Switzerland |
| Imprint: |
Springer International Publishing AG |
| Returns: |
Returnable |