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Item Details
Title: WAFER-LEVEL TESTING AND TEST DURING BURN-IN FOR INTEGRATED CIRCUITS
By: Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Format: Microfilm

List price: £109.00


We currently do not stock this item, please contact the publisher directly for further information.

ISBN 10: 1596939893
ISBN 13: 9781596939899
Publisher: ARTECH HOUSE PUBLISHERS
Pub. date: 1 February, 2010
Pages: 213
Synopsis: Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.
Illustrations: Illustrations
Publication: US
Imprint: Artech House Publishers
Returns: Non-returnable
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