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Item Details
Title: ALGORITHMS FOR SAMPLE PREPARATION WITH MICROFLUIDIC LAB-ON-CHIP
By: Sukanta Bhattacharjee
Format: Hardback

List price: £96.99
Our price: £87.29
Discount:
10% off
You save: £9.70
ISBN 10: 8770220557
ISBN 13: 9788770220552
Availability: Usually dispatched within 1-3 weeks.
 Delivery rates
Stock: Currently 0 available
Publisher: RIVER PUBLISHERS
Pub. date: 30 January, 2019
Series: River Publishers Series in Biomedical Engineering
Pages: 250
Returns: Returnable
Some other items by this author:
ADAPTIVE COOLING OF INTEGRATED CIRCUITS USING DIGITAL MICROFLUIDICS (HB)
ALGORITHMS FOR SAMPLE PREPARATION WITH MICROFLUIDIC LAB-ON-CHIP
ALGORITHMS, ARCHITECTURES AND INFORMATION SYSTEMS SECURITY (HB)
ANOMALY-DETECTION AND HEALTH-ANALYSIS TECHNIQUES FOR CORE ROUTER SYSTEMS
ANOMALY-DETECTION AND HEALTH-ANALYSIS TECHNIQUES FOR CORE ROUTER SYSTEMS (HB)
CISCO IP ROUTING PROTOCOLS (PB)
COMBINATORIAL IMAGE ANALYSIS (PB)
COMPUTER-AIDED DESIGN OF MICROFLUIDIC VERY LARGE SCALE INTEGRATION (MVLSI) BIOCHIPS (HB)
DATA-DRIVEN OPTIMIZATION AND KNOWLEDGE DISCOVERY FOR AN ENTERPRISE INFORMATION SYSTEM (HB)
DATA-DRIVEN OPTIMIZATION AND KNOWLEDGE DISCOVERY FOR AN ENTERPRISE INFORMATION SYSTEM (PB)
DESIGN AND TESTING OF DIGITAL MICROFLUIDIC BIOCHIPS (HB)
DESIGN AND TESTING OF DIGITAL MICROFLUIDIC BIOCHIPS (PB)
DESIGN AUTOMATION METHODS AND TOOLS FOR MICROFLUIDICS-BASED BIOCHIPS (HB)
DESIGN TECHNOLOGIES FOR GREEN AND SUSTAINABLE COMPUTING SYSTEMS (HB)
DESIGN TECHNOLOGIES FOR GREEN AND SUSTAINABLE COMPUTING SYSTEMS (PB)
DESIGN-FOR-TEST AND TEST OPTIMIZATION TECHNIQUES FOR TSV-BASED 3D STACKED ICS (HB)
DESIGN-FOR-TEST AND TEST OPTIMIZATION TECHNIQUES FOR TSV-BASED 3D STACKED ICS (PB)
DIGITAL MICROFLUIDIC BIOCHIPS
DIGITAL MICROFLUIDIC BIOCHIPS
DIGITAL MICROFLUIDIC BIOCHIPS
DIGITAL MICROFLUIDIC BIOCHIPS (HB)
DIGITAL MICROFLUIDIC BIOCHIPS (HB)
ENABLING IP ROUTING WITH CISCO ROUTERS (PB)
ERROR-TOLERANT BIOCHEMICAL SAMPLE PREPARATION WITH MICROFLUIDIC LAB-ON-CHIP
ERROR-TOLERANT BIOCHEMICAL SAMPLE PREPARATION WITH MICROFLUIDIC LAB-ON-CHIP (HB)
HARDWARE/SOFTWARE CO-DESIGN AND OPTIMIZATION FOR CYBERPHYSICAL INTEGRATION IN DIGITAL MICROFLUIDIC BIOCHIPS (HB)
HARDWARE/SOFTWARE CO-DESIGN AND OPTIMIZATION FOR CYBERPHYSICAL INTEGRATION IN DIGITAL MICROFLUIDIC BIOCHIPS (PB)
KNOWLEDGE-DRIVEN BOARD-LEVEL FUNCTIONAL FAULT DIAGNOSIS (HB)
MICRO-ELECTRODE-DOT-ARRAY DIGITAL MICROFLUIDIC BIOCHIPS (HB)
MICROELECTROFLUIDIC SYSTEMS
MICROELECTROFLUIDIC SYSTEMS (HB)
OPTIMIZATION OF TRUSTWORTHY BIOMOLECULAR QUANTITATIVE ANALYSIS USING CYBER-PHYSICAL MICROFLUIDIC PLATFORMS
OPTIMIZATION OF TRUSTWORTHY BIOMOLECULAR QUANTITATIVE ANALYSIS USING CYBER-PHYSICAL MICROFLUIDIC PLATFORMS (HB)
SCALABLE INFRASTRUCTURE FOR DISTRIBUTED SENSOR NETWORKS (HB)
SCALABLE INFRASTRUCTURE FOR DISTRIBUTED SENSOR NETWORKS (PB)
SECURE AND TRUSTWORTHY CYBERPHYSICAL MICROFLUIDIC BIOCHIPS
SECURE AND TRUSTWORTHY CYBERPHYSICAL MICROFLUIDIC BIOCHIPS (HB)
SECURITY OF BIOCHIP CYBERPHYSICAL SYSTEMS
SECURITY OF BIOCHIP CYBERPHYSICAL SYSTEMS (HB)
SOC (SYSTEM-ON-A-CHIP) TESTING FOR PLUG AND PLAY TEST AUTOMATION (HB)
SOC (SYSTEM-ON-A-CHIP) TESTING FOR PLUG AND PLAY TEST AUTOMATION (PB)
TEST AND DIAGNOSIS FOR SMALL-DELAY DEFECTS (HB)
TEST AND DIAGNOSIS FOR SMALL-DELAY DEFECTS (PB)
TEST INFRASTRUCTURE DESIGN
TESTING FOR SMALL-DELAY DEFECTS IN NANOSCALE CMOS INTEGRATED CIRCUITS
TESTING FOR SMALL-DELAY DEFECTS IN NANOSCALE CMOS INTEGRATED CIRCUITS (HB)
TESTING FOR SMALL-DELAY DEFECTS IN NANOSCALE CMOS INTEGRATED CIRCUITS (PB)
TESTING OF INTERPOSER-BASED 2.5D INTEGRATED CIRCUITS (HB)
WAFER-LEVEL TESTING AND TEST DURING BURN-IN FOR INTEGRATED CIRCUITS

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